Method of making stepped edge structure of an EEPROM tunneling w

Details Method of making stepped edge structure of an EEPROM tunneling w Method of making stepped edge structure of an EEPROM tunneling w

1997-06-30

1999-04-20

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438264, H01L 218247

Patent

active

058952403

ABSTRACT:
The present invention provides a structure and a method of forming a stepped trench oxide structure for a semiconductor memory device. The stepped trench oxide structure has "oxide steps" (e.g., 252 or 34A, 34B, 34C) in the gate oxide 20 surrounding the tunnel oxide layer 30. The oxide steps 34 are formed where the oxide thinning effect normally thins the tunnel oxide 30 around the perimeter of the tunnel oxide layer 30. The oxide steps 34 252 compensate for the oxide thinning effect and eliminate the problems associated with the oxide thinning effects. The oxide steps are preferably formed using one photo mask to form two different sized openings using different photoresist exposure times. The preferred method comprises forming a first tunneling opening 220A in a first (gate) oxide layer 220. Then, forming a second oxide layer 250 over said exposed substrate and said first oxide layer 220. A second opening 250A (smaller than the first opening) is formed in the second oxide layer thereby forming a first step 252. Next, a third oxide layer 270 is formed over said exposed substrate, the first oxide layer 220 and the second oxide layer 250 thereby propagating the first step 252. The oxide thinning edge effect is eliminated by the first step.

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