Method of defining gate structure height for semiconductor...

Details Method of defining gate structure height for semiconductor... Method of defining gate structure height for semiconductor...

2008-12-19

2010-11-16

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21176

Reexamination Certificate

active

07833853

ABSTRACT:
Provided is a method of semiconductor fabrication including process steps allowing for defining and/or modifying a gate structure height during the fabrication process. The gate structure height may be modified (e.g., decreased) at one or more stages during the fabrication by etching a portion of a polysilicon layer included in the gate structure. The method includes forming a coating layer on the substrate and overlying the gate structure. The coating layer is etched back to expose a portion of the gate structure. The gate structure (e.g., polysilicon) is etched back to decrease the height of the gate structure.

REFERENCES:
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patent: 7183596 (2007-02-01), Wu et al.
patent: 7195969 (2007-03-01), Chan et al.
patent: 2006/0128111 (2006-06-01), Beintner et al.
patent: 2007/0197009 (2007-08-01), Srivastava et al.
Chinese Patent Office, Office Action dated Jun. 28, 2010, Application No. 200910169153.8, 4 pages.

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