Method for testing embedded DRAM arrays

Details Method for testing embedded DRAM arrays Method for testing embedded DRAM arrays

2007-06-26

2007-06-26

Kerveros, James C (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000

Reexamination Certificate

active

10994496

ABSTRACT:
A system for testing a DRAM includes DRAM blocks, the system further includes a processor based built-in self test system for generating a test data pattern, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block. For each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time, and at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.

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