4. Excavating

Steven F. Oakland

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Access method for embedded JTAG TAP controller instruction...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Clock generator having improved deskewer

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate

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Clock signal latency elimination network

Pulse or digital communications – Spread spectrum – Direct sequence
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CMOS state saving latch

Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate

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Compilable memory structure and test methodology for both...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Profile ID: LFUS-PAI-P-443208

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