Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-08-23
2011-08-23
Dang, Phuc T (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S217000, C257S369000, C257SE21611
Reexamination Certificate
active
08003467
ABSTRACT:
The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.
REFERENCES:
patent: 7622341 (2009-11-01), Chudzik et al.
patent: 7691698 (2010-04-01), Chidambarrao et al.
patent: 2008/0191243 (2008-08-01), Liu et al.
Chang Maxi
Chen Chien-Liang
Chuang Harry
Fei Chung-Hau
Ng Jin-Aun
Dang Phuc T
Haynes and Boone LLP
Taiwan Semiconductor Manufacturing Company , Ltd.
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