Method for gap filling in a gate last process

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S231000, C438S275000, C438S591000, C438S595000, C257SE21434, C257SE21444

Reexamination Certificate

active

07923321

ABSTRACT:
A method is provided for fabricating a semiconductor device that includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the substrate, forming a silicon layer over the high-k dielectric layer, forming a hard mask layer over the silicon layer, patterning the hard mask layer, silicon layer, and high-k dielectric layer to form first and second gate structures over the first and second regions, respectively, forming a contact etch stop layer (CESL) over the first and second gate structures, modifying a profile of the CESL by an etching process, forming an inter-layer dielectric (ILD) over the modified CESL, performing a chemical mechanical polishing (CMP) on the ILD to expose the silicon layer of the first and second gate structures, respectively, and removing the silicon layer from the first and second gate structures, respectively, and replacing it with metal gate structures.

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patent: 7763532 (2010-07-01), Frohberg et al.
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