Method and apparatus for scan testing digital circuits

Details Method and apparatus for scan testing digital circuits Method and apparatus for scan testing digital circuits

1998-11-16

2000-11-07

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

061451053

ABSTRACT:
A method and digital system for testing scannable memory and combinational networks. The scannable memory is configurable into several scan chains. Each chain may have a different effective clock rate, as determined by respective clock enable signals. The method and digital system allow scan testing of digital circuits that use a single operational clock rate and several functional clock enable signals to effect slower lock operating rates. The digital system includes memory elements having scan enable and clock enable inputs.

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Kee Sup Kim and Len Schultz, "Multi-Frequency, Multi-Phase Scan Chain," IEEE International Test Conference 1994, Paper 11.1, pp. 323-330.

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