4. Static information storage and retrieval
  5. Read/write circuit
  6. Testing

Jean-Fran.cedilla.ois Cote

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Clock skew management method and apparatus

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Patent

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Method and apparatus for scan testing digital circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for testing multi-port memory using shadow

Static information storage and retrieval – Read/write circuit – Testing
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Profile ID: LFUS-PAI-P-591909

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