4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Dwayne Burek

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Hierarchical design and test method and system, program...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Method and apparatus for scan testing digital circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Method and apparatus for testing high performance circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Method and program product for designing hierarchical...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Method and program product for modeling circuits with latch...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate

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Profile ID: LFUS-PAI-P-1595438

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