State relaxation based subsequence removal method for fast stati

Details State relaxation based subsequence removal method for fast stati State relaxation based subsequence removal method for fast stati

Filed on

1997-12-31

Date issued

2000-11-07

Examiner

Nguyen, Hoa T.

Patent Class

Error detection/correction and fault detection/recovery

SubClass

Pulse or data error handling

SubSubClass

Digital logic testing

Other Related Categories

G01R 3128

Type

Patent

Status

active

Patent number

061451061

Description

ABSTRACT:
A method for fast static compaction in sequential circuits with finite output states by removing subsequences of test vectors from a vector test set. The method has the following steps: (1) relaxing the output states of the sequential circuits; (2) identifying a candidate subsequence of test vectors from the vector test set for removal; (3) temporarily removing the candidate subsequence of test vectors from the vector test set; (4) performing fault simulation on remaining test vectors from the vector test set; (5) examining fault simulation results against a set of removal criteria; (6) permanently removing the temporarily removed candidate subsequence if said set of removal criteria are met; (7) replacing the temporarily removed candidate subsequence if said set of removal criteria are not met; and (8) repeating steps (1) through (7) until all candidate subsequences of test vectors have been identified.

REFERENCES:
Pomeranz et al, "Verse: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuita", 1999 IEEE, pp. 250-255, Jul. 1999.
Bommu et al, "Vector restoration using accelerated validation and refinement", 1998 IEEE, pp. 458-466, Sep. 1998.
Hsiao et al., "Fast Static Compaction Algorithms for Sequential Circuit Test Vectors", IEEE Transactions On Computers, vol. 48, No. 3, Mar. 1999, pp. 311-322.
Pomeranz et al., "An Approach for Improving the Levels of CXompaction Achieved by Vector Omission", 1999 IEEE, pp. 463-466.
Higami et al, "Static Test Compaction for IDDQ Testing of Sequential CIrcuits", 1998 IEEE, pp. 9-13, 1999.

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