Memory test circuit and test system

Details Memory test circuit and test system Memory test circuit and test system

2007-07-03

2007-07-03

Lamarre, Guy (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S030000, C714S719000, C714S733000, C365S201000

Reexamination Certificate

active

10994140

ABSTRACT:
A memory test circuit comprises a memory which outputs stored data through n-bit data output pins, and a built-in self test (BIST) unit. The BIST unit writes test data in the memory, and by comparing the test data output from the memory with expected data, determines a failure cell address in the memory. The BIST unit generates k preliminary failure signals having failure information indicating whether the test data correspond with the expected data, and outputs the k preliminary failure signals for m cycles of a clock signal, by outputting k/m preliminary failure signals each cycle as first through k/m failure signals. In the memory test circuit and test system, the BIST unit testing a memory and generating a failure signal is disposed in a memory apparatus and a failure analysis circuit analyzing a failure signal output by the BIST unit is disposed in the test apparatus.

REFERENCES:
patent: 5910921 (1999-06-01), Beffa et al.
patent: 5912901 (1999-06-01), Adams et al.
patent: 5987632 (1999-11-01), Irrinki et al.
patent: 6085346 (2000-07-01), Lepejian et al.
patent: 6108252 (2000-08-01), Park
patent: 6163863 (2000-12-01), Schicht
patent: 6310807 (2001-10-01), Ooishi et al.
patent: 6408401 (2002-06-01), Bhavsar et al.
patent: 6421794 (2002-07-01), Chen et al.
patent: 6574763 (2003-06-01), Bertin et al.
patent: 6937531 (2005-08-01), Frankowsky
patent: 7013413 (2006-03-01), Kim et al.
patent: 2003/0014702 (2003-01-01), Finteis
patent: 2003/0177415 (2003-09-01), Togashi et al.
patent: 2005/0030822 (2005-02-01), Beer
patent: 2000-011691 (2000-01-01), None
patent: 2002-117697 (2002-04-01), None
patent: 01-27673 (2001-04-01), None

Affiliated with

Also associated with

Rating

Memory test circuit and test system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory test circuit and test system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory test circuit and test system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3819358