Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2009-11-13
2011-11-15
Garber, Charles (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S142000, C438S305000, C257SE21409
Reexamination Certificate
active
08058134
ABSTRACT:
An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.
REFERENCES:
patent: 6044203 (2000-03-01), Dawson et al.
patent: 7026229 (2006-04-01), Downey et al.
patent: 7223660 (2007-05-01), Hwang
patent: 2002/0119587 (2002-08-01), Tsai et al.
patent: 2004/0053457 (2004-03-01), Sohn
patent: 2006/0199345 (2006-09-01), Mineji
patent: 2009/0140351 (2009-06-01), Lin et al.
Sharp, J.A., et al., “Deactivation of Ultrashallow Boron Implants in Preamorphized Silicon After Nonmelt Laser Annealing with Multiple Scans,” Applied Physics Letters, 2006, 3 pages, vol. 89.
Cheng Nai-Han
Huang Li-Ping
Ku Keh-Chiang
Lin Yu-Chang
Wang Li-Ting
Garber Charles
Mustapha Abdulfattah
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
Junction profile engineering using staged thermal annealing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Junction profile engineering using staged thermal annealing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Junction profile engineering using staged thermal annealing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4291150