Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2002-09-25
2004-08-03
Le, Don (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C326S038000, C324S765010
Reexamination Certificate
active
06771093
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to test modes of semiconductor chips. More particularly, the present invention relates to the field of enabling a reference current measurement mode.
2. Related Art
The fabrication of semiconductor chips is a complex, expensive, and time-consuming task. A considerable amount of time is dedicated to testing the semiconductor chips. This testing occurs during a period known as sort or backend processing. The testing time for a semiconductor chip is carefully controlled because of several reasons. Production volume is affected by the testing time. In particular, a decrease in testing time increases production volume, positively affecting revenues. Conversely, an increase in testing time decreases production volume, negatively affecting revenues.
A number of tasks are performed during the testing of the semiconductor chip. Typically, the semiconductor chip is operated in a variety of test modes during the testing time. Typically, each test mode is individually invoked by performing a particular procedure. Another procedure is performed to exit the test mode. Generally, the currently active test mode is exited before another test mode is invoked.
Each test mode serves a particular purpose. For example, during testing a flash memory chip is typically operated in numerous test modes such as a reference current measurement mode, a reference array programming mode, and a reference array erase mode. These test modes facilitate parameter control and parameter characterization (e.g., threshold voltage V
t
) of an array of reference cells of the flash memory chip. Typically, the parameter characteristics of the memory cells of the flash memory chip are compared to the parameter characteristics of the array of reference cells to perform an operation such as a read operation.
Continuing, the reference array programming mode enables the threshold voltage V
t
of an array of reference cells of the flash memory chip to be programmed. The reference array erase mode enables the threshold voltage V
t
of the array of reference cells of the flash memory chip to be erased. Moreover, the reference current measurement mode enables the determination of the value of the threshold voltage V
t
of the array of reference cells of the flash memory chip by measuring a current flowing through the reference cells.
For instance, after the array of reference cells are programmed using the reference array programming mode, the reference array programming mode is exited so that the reference current measurement mode can be invoked to determine the value of the threshold voltage V
t
of the array of reference cells. In order to exit the reference array programming mode, high voltages applied to the flash memory chip so that to invoke the reference array programming mode need to be reset. Moreover, a test code corresponding to the reference current measurement mode needs to be provided to the flash memory chip. If the threshold voltage V
t
of the array of reference cells does not reach the desired level, the reference array programming mode needs to be re-invoked. This requires the inputting of a test code corresponding to the reference array programming mode and applying high voltages to the flash memory chip. This process may continue several more times. A similar situation exists after the array of reference cells is erased using the reference array erase mode. In sum, the conventional procedures for transitioning between the reference array programming mode and the reference current measurement mode and for transitioning between the reference array erase mode and the reference current measurement mode are tedious and inefficient.
SUMMARY OF THE INVENTION
A method of implementing a reference current measurement mode within a reference array programming mode or a reference array erase mode in a semiconductor chip is disclosed. This implementation leads to significant reduction in testing time for the semiconductor chip, increasing production volume and revenues.
In particular, either the reference array programming mode or the reference array erase mode is invoked in the semiconductor chip. This requires the application of high voltages and a test code to the semiconductor chip. Within the reference array programming mode (if invoked), the state of the output enable bar signal (or /OE) is changed (or pulsed) from a first state to a second state to enable the reference current measurement mode while disabling the reference array programming mode. Similarly, within the reference array erase mode (if invoked), the state of the output enable bar signal (or /OE) is changed (or pulsed) from a first state to a second state to enable the reference current measurement mode while disabling the reference array erase mode. Thus, the reference current measurement mode is enabled without requiring the high voltages to be reset and without requiring the test code corresponding to the reference current measurement mode to be provided to the semiconductor chip.
Conversely, the state of the output enable bar signal (or /OE) is changed (or pulsed) from the second state to the first state to enable the reference array erase mode (if previously invoked) or the reference array programming mode (if previously invoked) while disabling the reference current measurement mode. Again, the reference current measurement mode is disabled without requiring the high voltages to be reapplied and without requiring the test code corresponding to the reference array erase mode or the reference array programming mode to be provided again to the semiconductor chip. In an embodiment, the first state is a logic “high” while the second state is a logic “low”.
These and other advantages of the present invention will no doubt become apparent to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments, which are illustrated in the drawing figures.
REFERENCES:
patent: 6265859 (2001-07-01), Datar et al.
patent: 6329831 (2001-12-01), Bui et al.
patent: 6612737 (2003-09-01), Lobban
Bautista, Jr. Edward V.
Cheah Ken Cheong
Lee Weng Fook
Advanced Micro Devices , Inc.
Le Don
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