Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-05-08
2007-05-08
Kerveros, James C (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
10609254
ABSTRACT:
A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects.
REFERENCES:
patent: 5627841 (1997-05-01), Nakamura
patent: 6028983 (2000-02-01), Jaber
Jaber Talal K.
Lin Chih-Jen M.
Patil Srinivas
Reddy Madhukar K.
Sabbavarapu Anil K.
Caven & Aghevli LLC
Intel Corporation
Kerveros James C
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