Enhancement of silicon oxide etch rate and nitride...

Details Enhancement of silicon oxide etch rate and nitride... Enhancement of silicon oxide etch rate and nitride...

1999-03-25

2004-09-28

Olsen, Allan (Department: 1763)

Etching a substrate: processes

Gas phase etching of substrate

Application of energy to the gaseous etchant or to the...

C216S072000, C216S079000, C438S723000, C438S738000, C438S743000

Reexamination Certificate

active

06797189

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to etching of silicon integrated circuits. In particular, the invention relates to etching silicon oxide and related materials in a process that is capable of greatly reduced etching rates for silicon nitride and other non-oxide materials but still producing a vertical profile in the oxide.
BACKGROUND ART
In the fabrication of silicon integrated circuits, the continuing increase in the number of devices on a chip and the accompanying decrease in the minimum feature sizes have placed increasingly difficult demands upon many of the many fabrication steps used in their fabrication including depositing layers of different materials onto sometimes difficult topologies and etching further features within those layers.
Oxide etching has presented some of the most difficult challenges. Oxide is a somewhat generic term used for silica, particularly silicon dioxide (SiO
2
) although slightly non-stoichiometric compositions SiO
x
are also included, as is well known. The term oxide also covers closely related materials, such as oxide glasses including borophosphosilicate glass (BPSG). Some forms of silicon oxynitride are considered to more closely resemble an oxide than a nitride. Small fractions of dopants such as fluorine or carbon may be added to the silica to reduce its dielectric constant. Oxide materials are principally used for electrically insulating layers, often between different levels of the integrated circuit. Because of the limits set by dielectric breakdown, the thickness of the oxide layers cannot be reduced to much below 0.5 to 1 &mgr;m. However, the minimum feature sizes of contact and via holes penetrating the oxide layer are being pushed to well below 0.5 &mgr;m, the current developmental goal being 0.18 &mgr;m. The result is that the holes etched in the oxide must be highly anisotropic and must have high aspect ratios, defined as the depth to the minimum width of a hole. A further problem arises from the fact that the underlying silicon may be formed with active doped regions of thicknesses substantially less than the depth of the etched hole (the oxide thickness). Due to manufacturing variables, it has become impossible to precisely time a non-selective oxide etch to completely etch through the silicon oxide without a substantial probability of also etching through the underlying active silicon region.
The anisotropy can be achieved by dry plasma etching in which an etching gas, usually a fluorine-based gas, is electrically excited into a plasma. The plasma conditions may be adjusted to produce highly anisotropic etching in many materials. However, the anisotropy should not be achieved by operating the plasma reactor in a purely sputtering mode in which the plasma ejects particles toward the wafer with sufficiently high energy that they sputter the oxide. Sputtering is generally non-selective, and high-energy sputtering also seriously degrades semiconducting silicon exposed at the bottom of the etched contact hole.
In view of these and other problems, selective etching processes have been developed which depend more upon chemical effects. These processes are often described as reactive ion etching (RIE). The most popular active etching gas is a fluorocarbon (including hydrofluorocarbons) although some effort is being expended with other fluorinated gases such as SF
6
. A sufficiently high degree of selectivity allows new structures to be fabricated without the need for precise lithography for each level.
An example of such an advanced structure is a self-aligned contact (SAC), illustrated in the cross-sectional view of FIG.
1
. The illustrated SAC structure includes parts of two transistors formed on a silicon substrate
2
. A polysilicon gate layer
4
, a tungsten silicide barrier and glue layer
6
, and a silicon nitride cap layer
8
are deposited and photolithographically formed into two closely spaced gate structures
10
having a gap
12
therebetween. Chemical vapor deposition is then used to deposit onto the wafer a substantially conformal layer
14
of silicon nitride (Si
3
N
4
), which coats the top and sides of the gate structures
10
as well as a bottom
15
of the gap
12
. In practice, the nitride deviates from the indicated stoichiometry and may have a composition of SiN
x
, where x is between 1 and 1.5; the nitride acts as an electrical insulator. Dopant ions are ion implanted using the gate structures
10
as a mask to form a self-aligned p-type or n-type well
16
, which acts as a common source for the two transistors having respective gates
10
. The drain structures of the two transistors are not illustrated.
An oxide field layer
18
is deposited over this previously defined structure, and a photoresist layer
20
is deposited over the oxide layer
18
and photographically defined into a mask. A subsequent oxide etching step etches a contact hole
22
through the oxide layer
18
and stops on a portion
24
of the nitride layer
14
underlying the hole
22
. It is called a contact hole because the metal subsequently deposited into the contact hole
22
contacts underlying silicon rather than a metallic interconnect layer; the latter structure is called a via hole and is included within some aspects of the present invention. A soft post-etch plasma treatment removes the nitride portion
24
at the bottom
15
of the gap
12
. The silicon nitride acts as an electrical insulator between the gate structure
10
and the metal, usually aluminum, thereafter filled into the contact hole
22
.
Because the nitride acts as an insulator, the SAC structure and process offer the advantage that the contact hole
22
may be wider than the width of the gap
12
between the gate structures
10
. In advanced devices, the gap
12
between the gate structures
10
may be very small, less than 10 nm, while the width of the contact hole
22
may be significantly larger. Additionally, the photolithographic registry of the contact hole
22
with the gate structures
10
need not be precise. The imprecise definition of the mask in the photoresist layer
20
may place one side of the contact hole
22
near the middle of the gap
12
, as illustrated in
FIG. 2
, with a narrow side gap
26
forming at the bottom of the contact hole
22
on the side of one of the gate structures. The width of the side gap
26
may be 0.1 &mgr;m or less. Nonetheless, this may still provide a good contact. However, to achieve these beneficial effects, the SAC oxide etch must be highly selective to nitride. That is, the process must produce an oxide etch rate that is much greater than the nitride etch rate. Numerical values of selectivity are calculated as the ratio of the oxide to nitride etch rates. Selectivity is especially critical at corners
28
of the nitride layer
14
above and next to the gap
12
or
26
since the nitride corners
28
are the portion of the nitride exposed the longest to the oxide etch. Furthermore, they have a geometry favorable to fast etching that tends to create facets at the nitride corners
28
. The corners of the gate structures
10
will thereby be prematurely exposed if the faceting is severe enough.
Furthermore, increased selectivity is being required with the increased usage of chemical mechanical polishing (CMP) for planarization of an oxide layer over a curly wafer. The polishing planarization produces a flat top surface in the oxide layer over the wavy underlying substrate, thereby producing an oxide layer of significantly varying thickness. To compensate for this variable thickness, the time of the oxide etch must be set significantly higher, say by 100%, than the etching time for the design thickness to assure penetration of the variable thickness oxide. This extra etching time is called over etch, which also accommodates other process variations. However, for the regions with a thinner oxide, the nitride is exposed that much longer to the etching environment.
Ultimately, the required degree of selectivity is reflected in the probability of an electrical short through the nitride layer
14
bet

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