CVD deposition method to improve adhesion of F-containing...

Details CVD deposition method to improve adhesion of F-containing... CVD deposition method to improve adhesion of F-containing...

1997-10-10

2001-11-27

Meeks, Timothy (Department: 1762)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S628000, C438S778000, C438S780000, C438S783000, C427S249100, C427S535000, C427S576000, C427S577000, C427S250000, C427S255391, C427S255394, C204S192170

Reexamination Certificate

active

06323119

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates generally to the deposition of an amorphous fluorocarbon film using a high density plasma chemical vapor deposition (HDP-CVD) technique. More particularly, the present invention relates to a method of depositing an amorphous fluorocarbon film using a high bias power to enhance gap fill performance. Still further, the invention relates to improving adhesion of a fluorine containing dielectric material to metal surfaces formed on a substrate.
BACKGROUND OF THE INVENTION
Consistent and fairly predictable improvement in integrated circuit design and fabrication has been observed in the last decade. However, for newer ultra large scale integration (ULSI) products with operation frequencies approaching 1 GHz and interconnect feature sizes decreasing to ≦0.25 &mgr;m, interconnect resistance-capacitance (RC) delay will represent a large portion of the clock time of integrated circuits, and significantly new and different manufacturing approaches will be required to achieve the required performance goals. Since RC delay is directly related to the interconnect resistance and dielectric capacitance, the industry focus is on developing new materials with significantly lower dielectric constants and lower resistivities.
In the area of dielectrics, a great variety of materials are being investigated as potential replacements for the current standard silicon dioxide (SiO
2
). If SiO
2
, which has a dielectric constant (K)~4, is replaced by another material with a K value of ~2.5, RC delay and cross talk will be significantly reduced and overall circuit performance will be greatly improved. It is well accepted that a dielectric constant of <3.0 will be required at the 0.18 &mgr;m device generation in order to meet expected performance requirements.
A great variety of materials with low dielectric constants are being investigated as potential candidates to replace SiO
2
. However, it is important to remember that dielectric constant is but one of the critical requirements that must be met. Ease of integration into existing and future process fabrication flows and economic factors (e.g., cost of ownership) will together decide the viability of a material for use as the next generation intermetal dielectric (IMD). Integration capability will be determined by critical properties such as adhesion, thermal stability, thermal conductivity, mechanical strength and gap fill performance. Cost of ownership will be determined by cost of the raw materials, cost of processing waste material (which has been found to be especially high with spin-on techniques), the number of required integration steps as well as the capital cost of the processing equipment. The ideal low dielectric constant material will easily integrate into existing process flows, will use existing equipment, and cost no more than processes in use today.
CVD-deposited materials are the most promising approach for low dielectric constant materials. It is well accepted that the mechanisms in plasma assisted depositions will lead to materials with significantly higher density and mechanical strength than other types of deposition techniques. In addition, integration of a CVD film is well characterized and fairly simple as compared with wet processes such as spin-on methods. The potential of using existing plasma enhanced CVD equipment and simple manufacturing methodology makes CVD materials attractive from both an integration and an economic standpoint.
Among the CVD-deposited materials, amorphous fluorocarbon (&agr;-FC) is promising for its relatively high thermal stability, low dielectric constant value (as low as 2.3), thermal conductivity close to that of SiO
2
, and good mechanical strength. Recently, Matsubara et al., “Low-k Fluorinated Amorphous Carbon Interlayer Technology for Quarter Micron Devices”, IEDM, p 369-372 (1996), have described the successful integration and use of &agr;-FC as the intermetal dielectric in a three-level metallization structure. A 50% decrease in line capacitance is reported using this dielectric material.
However, as geometries shrink, gap fill performance becomes a significant issue. Gap fill performance generally refers to the ability of a process to fill the area, known as trenches, between metal lines. Recently, the trend has been to incorporate high density plasma processes into integrated sequences to take advantage of in situ sputter etch and deposition to achieve enhanced gap fill results. In HDP-CVD, a bias power is coupled to the substrate to attract ions which sputter the field of the substrate during deposition, thereby preventing a phenomena known as crowning where the deposition material converges over the trench before the trench is completely filled with the deposition material. By controlling the deposition rate on the field (i.e., the area between the trenches) of the substrate, improved gap fill performance in small features ≦0.25 &mgr;m can be achieved.
One problem associated with &agr;-FC films is that application of a high bias power tends to enhance fragmentation of fluorine which is then incorporated into the resulting film as loose unbonded F or CF
x
(x=1-4). It has been well documented that organic fluorocarbon molecules will either form etching species such as F
−
or polymerize under glow discharge conditions. Whether etching or the polymerization reaction will dominate depends on plasma energy, charged specie intensities, reactant ratios and surface temperatures. EP patent application Ser. No. 5114253.8 discusses the problems associated with high bias power and attempts to resolve the problems by eliminating the use of high bias power in the depositin of an &agr;-FC film.
Another problem encountered is that fluorine generated during deposition of the fluorine containing dielectric materials is adsorbed by the chamber walls and chamber components and is out gassed during subsequent deposition steps. The fluorine attacks the metal surfaces on the substrate and prevents good adhesion. Titanium, nitride is frequently used as a barrier layer between dielectric layers and metal layers and is somewhat resistant to diffusion of process gases. However, titanium nitride does not substantially improve adhesion between the metal surfaces and the fluorine containing dielectric materials.
Therefore, there is a need to improve the application of HDP-CVD technology for deposition of very low dielectric constant &agr;-FC films. It would be advantageous to provide an &agr;-FC film having a dielectric constant (k) of 2.8 or less which can be deposited using high density plasma deposition, exhibits good gap fill performance in features 0.25 &mgr;m and smaller and which is stable with a single post deposition anneal.
SUMMARY OF THE INVENTION
The present invention provides a method of forming an amorphous fluorocarbon film having both thermal stability and a low dielectric constant. The method comprises the steps of introducing a substrate into a process chamber and positioning the substrate on a support member connected to a bias power source, introducing a carbon source gas and a fluorine source gas into the process chamber, delivering a source power to the chamber sufficient to strike a plasma in the chamber, and applying a bias power to the support member at a power level sufficient to achieve in situ sputter deposition on the substrate. The carbon gas source and fluorine gas source are preferably introduced in sufficient amount to maintain an atomic ratio of F:C less than 2.
Another aspect of the invention provides a season coating of silicon nitride or silicon oxynitride on internal surfaces of the deposition chamber prior to substrate processing to prevent out gassing of fluorine or fluorine compounds from the chamber surfaces. In one embodiment, silicon nitride or silicon oxynitride is deposited on internal surfaces of a deposition chamber in an amount sufficient to block out gassing of fluorine from the internal surfaces. The amount of outgassed fluorine can be controlled to prevent unwan

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