Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-01-23
2007-01-23
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S738000, C714S030000
Reexamination Certificate
active
10906047
ABSTRACT:
An integrated circuit device can be tested using a built-in test circuit, in the IC device, that tests the operation of an I/O cell. The built-in test circuit includes a pattern generator for generating a series of simulation signals. The built-in test circuit successively stores and retrieves the simulation signals from an I/O buffer of the I/O cell. For each iteration of storing and retrieving, test logic of the built-in test circuit compares the stored and retrieved data to check whether the data matches. If a mismatch is detected, the test logic issues a fail signal. The fail signal can cause a unique signal at the pad of the I/O cell that alerts a tester to the failure of the IC device. The fail signal can also cause the issuance of a device failure signal that can be detected at other pins of the IC device.
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Lamarre Guy
Taiwan Semiconductor Manufacturing Company , Ltd.
Trimmings John P.
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