4. Static information storage and retrieval
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External clock tracking pipelined latch scheme

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate

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External clock tracking pipelined latch scheme

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate

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External compensation apparatus and method for fail bit dynamic

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Externally clocked electrical fuse programming with...

Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate

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Externally controlled power on reset device for non-volatile mem

Static information storage and retrieval – Read/write circuit – Signals
Patent

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Extra row for testing programmability and speed of ROMS

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Extraction of a binary code based on physical parameters of...

Static information storage and retrieval – Read/write circuit – Particular read circuit
Reexamination Certificate

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