External compensation apparatus and method for fail bit dynamic

Details External compensation apparatus and method for fail bit dynamic External compensation apparatus and method for fail bit dynamic

1995-12-27

1997-06-17

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Bad bit

36518907, G11C 700

Patent

active

056403534

ABSTRACT:
An apparatus and method for bit defect compensation is disclosed which comprises a tag address means for storing addresses of defective bits of a DRAM; a compensation data means for storing replacing bits utilized to replace the defective bits; a control circuit that provides logic and timing controls for compensation actions; and a comparator that provides comparison function between DRAM access address and addresses stored in the tag address means, and generates a compensation address to access the replacing bits in the compensation data means when necessary. The present invention provides an improved apparatus and method for compensating for the problem of bit defect, and improving the traditional fail bit memory scheme.

REFERENCES:
patent: 4757474 (1988-07-01), Fukushi et al.
patent: 4803656 (1989-02-01), Takemae
patent: 5195057 (1993-03-01), Kasa et al.

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