External clock tracking pipelined latch scheme

Details External clock tracking pipelined latch scheme External clock tracking pipelined latch scheme

2008-12-08

2009-10-27

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S233500

Reexamination Certificate

active

07609565

ABSTRACT:
A flash memory including a first latch having at least one external input to receive at least one command, at least one memory address, and a plurality of data bits, a command decoder coupled to the first latch output; a command latch including a first command latch input, a second command latch input, and a command latch output, the first command latch input to couple to the command decoder output, and the second command latch input to couple to a write command output of an internal clock control generator; and a command register including a first command register input and a second command register input, the first command register input to couple to the command latch output, and the second command register input to couple to an internal latch command output of the internal clock control generator. Additional apparatus, systems, and methods are disclosed.

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Lee, J., et al., “A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications”,IEEE Journal of Solid-State Circuits, 38(11), (Nov. 2003), 1934-1942.
Lee, June, et al., “High-performance 1-Gb-NAND flash memory with 0.12-/spl mu/m technology”,IEEE Journal of Solid-State Circuits, 37(11), (Nov. 2002), 1502-1509.

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