Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1985-10-15
1988-04-26
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
365201, G11C 700
Patent
active
047409258
ABSTRACT:
A method of making an array of programmable read only semiconductor memory cells which includes forming an extra row of the memory cells and a corresponding extra row gate coupled thereto. Extra row gate enabling means is coupled to the extra row gate for enabling the extra row gate in response to a control signal KILLT applied thereto. A disabling means is coupled to a first selected row gate other than the extra row gate in order to disable the selected row gate in response to a control signal KILLT applied thereto. A disabling means is coupled to a first selected row gate other than the extra row gate in order to disable the selected row gate in response to the control signal KILLT being applied thereto.
An NAND gate may be formed with the extra row gate to allow a second set of signals corresponding to a second selected row of memory cells to enable the second selected row gate. A disabling means is coupled to the second selected row gate other than the extra row gate. In response to a control signal KILLB being applied to both the NAND gate and to the gate of the second selected row, it is possible to use the second selected row to test the first selected row and vice versa.
REFERENCES:
patent: 4358833 (1982-11-01), Folmsbee et al.
patent: 4365319 (1982-12-01), Takemae
patent: 4571707 (1986-02-01), Watanabe
patent: 4639897 (1987-01-01), Wacyk
Coffman Timmie M.
Kaszubinski Jeffrey K.
Schreck John F.
Wilmoth David D.
Anderson Rodney M.
Graham John G.
Popek Joseph A.
Texas Instruments Incorporated
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