Reducing phase offsets in a phase detector
Reducing waiting time jitter
Reducing waiting time jitter
Redundant clock generation and distribution
Reference timing signal oscillator with frequency stability
Register controlled delay locked loop circuit
Reliable switching between data sources in a synchronous communi
Reset circuit and pll frequency synthesizer
Residual phase error correction
Resistorless phase locked loop circuit employing direct current
Retiming method and means
Robust phase estimator and recoverer for digital signals affecte
RZ recovery