Reducing phase offsets in a phase detector

Details Reducing phase offsets in a phase detector Reducing phase offsets in a phase detector

2004-12-28

2009-08-18

Fan, Chieh M (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S371000, C375S376000

Reexamination Certificate

active

07577224

ABSTRACT:
In one embodiment, the present invention includes a system having an amplifier to receive an incoming signal and a recovery circuit coupled to the amplifier that includes a phase detector to adjust a phase of a sampling clock via a signal indicative of a difference between transitions occurring between the sampling clock and each of a first error clock and a second error clock. Based on a phase adjusted output of the phase detector, the sampling clock may be generated with an appropriate phase. Thus, circuitry and methods are provided to reduce or eliminate phase offsets in the phase detector.

REFERENCES:
patent: 5182761 (1993-01-01), Beyer et al.
patent: 6178213 (2001-01-01), McCormack et al.
patent: 6188737 (2001-02-01), Bruce et al.
patent: 6236696 (2001-05-01), Aoki et al.
patent: 6324144 (2001-11-01), Won et al.
patent: 6463109 (2002-10-01), McCormack et al.
patent: 6630868 (2003-10-01), Perrott et al.
patent: 6657488 (2003-12-01), King et al.
patent: 6741846 (2004-05-01), Welland et al.
patent: 6856206 (2005-02-01), Perrott
patent: 6876240 (2005-04-01), Moon et al.
patent: 7076377 (2006-07-01), Kim et al.
patent: 7164742 (2007-01-01), McLeod
patent: 7190742 (2007-03-01), Popescu et al.
patent: 7292670 (2007-11-01), Gupta et al.
patent: 7349507 (2008-03-01), Maddux
patent: 2004/0232995 (2004-11-01), Thomsen et al.
patent: 2005/0147197 (2005-07-01), Perrott
patent: 2005/0265487 (2005-12-01), Sou
patent: 2006/0045224 (2006-03-01), Cranford et al.
patent: 2006/0140321 (2006-06-01), Tell et al.
patent: WO 2004/100380 (2004-11-01), None
Sang-Hyun Lee, Moon-Sang Hwang, Youngdon Choi, Sungjoon Kim, Yongsam Moon, Bong-Joon Lee, Deog-Kyoon Jeong, Wonchan Kim, Young-June Park, Gijung Ahn, “A 5-Gb/s 0.25-μm CMOS Jitter-Tolerant Variable-Interval Oversampling Clock/Data Recovery Circuit”, IEEE Journal of Solid State Circuits, vol. 37, No. 12, Dec. 2002.
Bong-Joon Lee, Moon-Sang Hwang, Sang-Hyun Lee, and Deog-Kyoon Jeong, “A 2.5-10-GB/s CMOS Transceiver With Alternating Edge-Sampling Phase Detection for Loop Characteristic Stabilization”, IEEE Journal of Solid-State Circuits, vol. 38, No. 11, Nov. 2003.
“A 5-Gb/s 0.25μm CMOS Jitter-Tolerant Variable-Interval Oversampling Clock/Data Recovery Circuit”. Lee, Sang-Hyun; Moon-Sang Hwang, Youngdon Choi, Sungjoon Kim, Young-June Park, and Gijung Ahn.IEEE Journal Of Solid-State Circuits, vol. 37, No. 12, pp. 1822-1830. Dec. 2002.
“Rate-Independent CDR Chip Locks In At Up To 2.7 Gbits/s”. Mannion, Patrick.Electronic Design. www.elecdesign.com. Mar. 20, 2000.
OC-48 Optical Networking Solutions—Solutions Guide. Silicon Laboratories. May 2003.
Si5022/23 Multi-Rate Sonet/SDH CDR IC with Integrated Limiting Amplifier—Product Brief. Silicon Laboratories. May 2001.
Si5010—Product Brief. Silicon Laboratories. Dec. 2004.
“Data conversion in SONET/SDH systems”, A. Muhlschein. Electronics Engineer. Jun. 2000.

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