Reset circuit and pll frequency synthesizer

Details Reset circuit and pll frequency synthesizer Reset circuit and pll frequency synthesizer

2000-03-10

2004-09-21

Tse, Young T. (Department: 2734)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S354000

Reexamination Certificate

active

06795516

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a PLL frequency synthesizer which matches the frequency of an output signal with a set frequency, and an optimal reset circuit for the PLL frequency synthesizer.
In recent years, PLL frequency synthesizers have been employed in mobile communication devices, such as cellular phones. A mobile communication device uses two frequency bands. The interval between each frequency is large. Thus, a voltage-controlled oscillator (VCO), which forms a PLL synthesizer, cannot handle frequency fluctuations. Accordingly, the PLL synthesizer is provided with a reset circuit for temporarily stopping the operation until the VCO stabilizes. Further, the PLL frequency synthesizer has a power-save function to reduce power consumption so that the battery of the mobile communication device lasts longer. The PLL frequency synthesizer provided with such functions must also be capable of immediately switching the frequency of an output signal to a desired one to improve performance of the mobile communication device.
FIG. 6
is a schematic block diagram showing a prior art PLL frequency synthesizer
10
including a reset circuit and provided with a power-save function.
A reference oscillator
11
provides a reference oscillation signal fosc to a reference counter
13
and an initial phase detector
14
via an input buffer
12
. A comparison oscillation signal fin is divided by a comparison signal divider
15
and provided to a main counter
16
and the initial phase detector
14
. The reference counter
13
divides the reference oscillation signal fosc based on a predetermined reference dividing ratio and provides a resulting divided signal, i.e., reference signal fr, to a phase comparator
17
. The comparison signal divider
15
divides the comparison oscillation signal fin based on a predetermined dividing ratio and provides a resulting divided signal fpp to the main counter
16
. The main counter
16
divides the divided signal fpp based on a predetermined comparison dividing ratio and provides a resulting divided signal, i.e., comparison signal fp, to the phase comparator
17
.
The initial phase detector
14
receives the reference oscillation signal fosc and the divided signal fpp. If the reference oscillation signal fosc goes high during a predetermined period from when the divided signal fpp goes high, the initial phase detector
14
sends a command signal to the reference counter
13
and the main counter
16
to enable operation of the counters
13
,
16
. On the other hand, if the reference oscillation signal fosc remains low during the predetermined period from when the divided signal fpp goes high, the initial phase detector
14
provides the reference counter
13
and the main counter
16
with a command signal that inhibits operation of the counters
13
,
16
.
The phase comparator
17
receives the reference signal fr and the comparison signal fp to compare the rising edge of the reference signal fr with that of the comparison signal fp. The phase comparator
17
provides a pulse signal, which corresponds to the frequency difference and phase difference of the signals fr, fp, to a charge pump
18
. A pull-up transistor or pull-down transistor of the charge pump
18
is activated based on the pulse signal from the phase comparator
17
. A low-pass filter
19
connected to the charge pump
18
functions as a load applied to the charge pump
18
. In the charge pump
18
, activation of the pull-up transistor increases the output voltage, and activation of the pull-down transistor decreases the output voltage.
The low-pass filter
19
smoothes the output voltage of the charge pump
18
and sends the smoothed output voltage to a voltage control oscillator (VCO)
20
. The VCO
20
generates a frequency output signal fvco corresponding to the output voltage of the low-pass filter
19
. The output signal fvco is used as a transmission wave of the communication device. Further, the output signal fvco is provided to the comparison signal divider
15
as the comparison oscillation signal fin.
The PLL frequency synthesizer
10
locks the output signal fvco, which is used as a transmission wave, to a frequency corresponding to the reference dividing ratio of the reference counter
13
and the comparison dividing ratio of the main counter
16
.
The PLL frequency synthesizer
10
also includes a reset circuit
51
. The reset circuit
51
receives the reference signal fr from the reference counter
13
, as a delayed clock CLK, and a frequency setting signal DIV.
FIG. 7
is a block diagram showing the reset circuit
51
.
The reset circuit
51
includes a delay circuit
52
and an exclusive NOR circuit
53
. The delay circuit
52
has three D flip-flops (DFFs)
52
a
-
52
c
. Each of the DFFs
52
a
-
52
c
has a clock input terminal C, which receives the delayed clock CLK (reference signal fr) shown in FIG.
6
. The first DFF
52
a
has a data input terminal D for receiving the frequency setting signal DIV and an output terminal Q connected to a data input terminal D of the second DFF
52
b
. The second DFF
52
b
has an output terminal Q connected to a data input terminal D of the third DFF
52
c.
The frequency setting signal DIV, which is provided by an external device, is a signal inverted between a high level and a low level each time the frequency of the output signal fvco generated by the PLL frequency synthesizer
10
changes.
More specifically, with reference to
FIG. 8
, subsequent to the rising of the frequency setting signal DIV and in response to a first pulse of the delayed clock CLK, the first DFF
52
a
holds the frequency setting signal DIV at the high level and outputs the frequency setting signal DIV (output signal SGA) from the output terminal Q. Then, when a second pulse of the delayed clock CLK is output, the second DFF
52
b
holds the output signal SGA, which is held and output by the first DFF
52
a
, at the high level and outputs the output signal SGA (output signal SGB) from the output terminal Q. Afterward, when a third pulse of the delayed clock CLK is output, the third DFF
52
a
holds the output signal SGB, which is held and output by the second DFF
52
b
, and outputs the output signal SGB (output signal SGC) from the output terminal Q.
Accordingly, the delay circuit
52
, which includes the DFFs
52
a
-
52
c
, acts as a shift register. If the level of the input frequency setting signal DIV shifts, the shift register shifts the level of the output frequency setting signal DIV (output signal SGC) when receiving three pulses of the delayed clock CLK subsequent to the level shift of the input frequency setting signal DIV.
The exclusive NOR circuit
53
receives the output signal SGC from the delay circuit
52
and the frequency setting signal DIV. If the level of the output signal SGC matches that of the frequency setting signal DIV, the exclusive NOR circuit
53
causes a reset signal, i.e., output signal OUT, to go high. If the level of the output signal SGC does not match that of the frequency setting signal DIV, the exclusive NOR circuit
53
causes the reset signal, i.e., output signal OUT, to go low. Therefore, when the level of the frequency setting signal DIV changes, the output signal OUT of the exclusive NOR circuit
53
is low from when the level changes to when three pulses of the delayed clock CLK are received.
The output signal OUT of the reset circuit
51
is provided to an internal circuit, i.e., the phase comparator
17
. The phase comparator
17
is activated when the output signal OUT is high and deactivated when the output signal OUT is low. Thus, the phase comparator
17
stops operation (initialization) whenever the frequency setting signal DIV changes until three pulses of the delayed clock CLK have been received. That is, during the period from when the set frequency changes to when the VCO
20
stabilizes in response to the change, the reset circuit
51
temporarily stops operation (initialization) of the phase comparator
17
and deactivates the PLL frequency synthesizer
10
.
Further, the P

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