Redundant clock generation and distribution

Details Redundant clock generation and distribution Redundant clock generation and distribution

1999-06-12

2004-06-29

Tran, Khai (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

06757350

ABSTRACT:

FIELD OF THE INVENTION
This invention is directed to the class of redundant clock generation where a plurality of phase synchronous clocks is distributed to a plurality of loads, whereby a failure in or removal of one clock source does not effect the operation of the system.
BACKGROUND OF THE INVENTION
There are many prior art methods of generating and selecting a clock for use in a system with redundant clock sources. In one class of redundant clock generation, no attempt is made to directly synchronize the plurality of available clock sources. Instead, a post-clock synchronizer circuit is provided to maintain clock phase. Examples of this type of system include U.S. Pat. No. 5,522,915 by Byers et al, which identifies the synchronizer as elements
64
and
66
of
FIG. 3
of this reference. U.S. Pat. No. 5,570,397 by Kubista discloses non-locked oscillators, a phase comparison circuit, and a pair of synchronizers which modify the respective oscillator inputs to produce a pair of synchronized clock outputs. U.S. Pat. No. 5,371,764 by Gillingham et al includes a variable delay element for adjusting the phase of the secondary clock.
Another class of clocking system relies on a master-slave relationship between the oscillators. In this topology, one of the clock sources is selected as the master, and the other the slave, which phase locks to the selected master. The roles of master and slave may reverse according to external control signals. U.S. Pat. No. 4,282,493 by Moreau is one such example. The slave oscillator tracks the master oscillator with a minimum of phase error. In the event that the master is determined to be defective, the defective master oscillator may be disabled, and the slave may replace the defective master for output signals. Another example of a master slave topology is U.S. Pat. No. 5,355,090 by Pajowski discloses Master Clock oscillators MC
1
and MC
2
, and Phase Correctors PC
1
and PC
2
operate to track either MC
1
or MC
2
, according to control signals provided by a microprocessor.
Another class of clock generation circuits produces a plurality of phase locked signals without a master-slave relationship, where a plurality of oscillator sources are cross-coupled to produce a plurality of phase coherent signals. One example of such a system is described in U.S. Pat. No. 5,557,623 by Discoll, and another example is U.S. Pat. No. 4,779,008 by Kessels. Both references disclose an oscillator having variable delay elements and phase alignment circuitry for adjusting the frequency and phase to a phase coherent state.
OBJECTS OF THE INVENTION
A first object of the invention is to provide a clock generation circuit comprising a plurality of oscillators which lock in phase to each other and also operate at the center frequency of the oscillator. A second object of the invention is to provide a clock selection circuit which provides for transient-free clock switchover.
SUMMARY OF THE INVENTION
In a first embodiment, a local clock circuit and a remote clock circuit are cross coupled. The local and remote clock circuits are identical in internal design and function, so any clock circuit may be observed from the perspective of a local clock circuit. Each clock circuit comprises a voltage controlled oscillator (VCO) coupled to a phase comparator producing a phase error proportional to the phase difference between the local oscillator and the remote oscillator. This local phase error is then processed by a cost function, which produces a control voltage provided to a local voltage controlled oscillator. The cost function comprises a linear combination of three error terms: a first phase error multiplied by a phase error gain, a second deviation from center frequency error multiplied by a deviation gain, and a third temporally varying offset. The cost function may be a linear or non-linear combination of these terms, and produces a control output for use by the voltage controlled oscillator.
In another embodiment, a local clock oscillator may be cross-coupled to a plurality of remote clock oscillators. As before, each clock oscillator comprises a voltage controlled oscillator coupled to a plurality of phase comparators, each producing a phase error proportional to the phase difference between the local oscillator and each of the remote oscillators. This local phase error is then processed by a cost function, which produces an error voltage provided to the local voltage controlled oscillator. The cost function comprises a linear combination of each phase comparator phase error term multiplied by a phase error gain, the deviation from center frequency, multiplied by a deviation gain, and a variable offset. The cost function may be a linear or non-linear combination of these terms.


REFERENCES:
patent: 4239982 (1980-12-01), Smith et al.
patent: 4282493 (1981-08-01), Moreau
patent: 4779008 (1988-10-01), Kessels
patent: 5036528 (1991-07-01), Le et al.
patent: 5295258 (1994-03-01), Jewett et al.
patent: 5355090 (1994-10-01), Pajowski et al.
patent: 5371764 (1994-12-01), Gillingham et al.
patent: 5422915 (1995-06-01), Byers et al.
patent: 5510397 (1996-04-01), Okuda et al.
patent: 5537583 (1996-07-01), Truong
patent: 5557623 (1996-09-01), Discoll
patent: 5642069 (1997-06-01), Waite
patent: 6194969 (2001-02-01), Doblar
patent: 6204732 (2001-03-01), Rapoport et al.
patent: 6239626 (2001-05-01), Chesavage
patent: 6516422 (2003-02-01), Doblar et al.

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