Gated clock circuit with a substantially increased control...
Gated clock tree synthesis method for the logic design
Gated-clock registers for low-power circuitry
Gating for dual edge-triggered clocking
Generating a clock signal
Generating a pulse signal with a modulated duty cycle
Generating circuit including selection between plural phase regu
Glitch free clock multiplexer that uses a delay element to...
Glitch free clock multiplexer that uses a delay element to...
Glitch-free clock multiplexer that provides an output clock...
Glitchless clock switching circuit
Glitchless pulse generator