Gated clock circuit with a substantially increased control...

Details Gated clock circuit with a substantially increased control... Gated clock circuit with a substantially increased control...

2006-05-09

2006-05-09

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S294000, C327S299000

Reexamination Certificate

active

07042267

ABSTRACT:
A gated clock circuit outputs a gated clock signal in response to a master clock signal and a control signal that has a rising or falling edge that follows a rising edge of the master clock signal by a delay. The gated clock signal has a pulse width that is equal to, and in phase with, the pulse width of a master clock signal, while at the same time substantially increasing the maximum value of the delay.

REFERENCES:
patent: 5475322 (1995-12-01), MacDonald
patent: 5886582 (1999-03-01), Stansell
patent: 5892373 (1999-04-01), Tupuri et al.
patent: 6242960 (2001-06-01), Bae
patent: 6320437 (2001-11-01), Ma
patent: 6496554 (2002-12-01), Ahn
patent: 6552572 (2003-04-01), Cheung et al.
patent: 6566924 (2003-05-01), Lin et al.

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