Generating a clock signal

Details Generating a clock signal Generating a clock signal

1999-12-29

2003-06-17

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S299000, C327S158000

Reexamination Certificate

active

06580305

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to generating a clock signal.
Clocking circuitry for electronic devices, such as a slave RAC (RAMBUS Application-Specific Integrated Circuit Cell), generates clock signals based on a master clock. Typically, the master clock is a strobe clock, such as a CTM or Clock To Master, for sampling data received from a transmission line. The strobe clock runs about 90 degrees out of phase with the leading edge of the data so that the center of each bit is sampled. By contrast, the data is clocked to/from an electronic device at roughly one “tco” earlier than the leading edge of a bit, where “tco” corresponds to the delay between a data clock and valid output data, which is usually an output buffer delay. The data clock is therefore 90 degrees out of phase with the master clock. Clocking circuitry in the device is used to preserve this phase relationship between the master clock and the data clock.
SUMMARY OF THE INVENTION
In general, in one aspect, the invention relates to generating a clock signal. This aspect of the invention features generating a first clock signal based on a first set of reference clocks, selecting a second set of reference clocks based on the first clock signal and a predetermined delay, and generating a second clock signal, based on the second set of reference clocks, which substantially compensates for the predetermined delay.
Among the advantages of this aspect of the invention may be one or more of the following. Generating the second clock signal based on the first clock signal makes it possible to obtain a proper phase relationship between the second clock signal and a master clock signal. Moreover, taking into account a predetermined delay in the second clock signal reduces phase discrepancies brought about, e.g., by hardware such as input/output (I/O) buffers and package trace delays. A digital control circuit may be used to introduce the predetermined delay. Use of a digital control circuit reduces phase errors that may be introduced from less reliable circuitry.
Other features and advantages of the invention will become apparent from the following description, drawings, and claims.


REFERENCES:
patent: 5663767 (1997-09-01), Rumreich et al.
patent: 5982212 (1999-11-01), Kobayashi
patent: 5994938 (1999-11-01), Lesmeister
patent: 6100733 (2000-08-01), Dortu et al.
patent: 6252443 (2001-06-01), Dortu et al.

Affiliated with

Also associated with

Rating

Generating a clock signal does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Generating a clock signal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Generating a clock signal will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3161229