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Microprocessor with trace module

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Microprocessor with trace module

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Microprocessor-based device incorporating a cache for capturing

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent

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Migrating a virtual machine in response to failure of an...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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MIMO hybrid-ARQ using basis hopping

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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MIMO transmitting apparatus, MIMO receiving apparatus, and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Minimizing data loss in asynchronous replication solution...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Minimizing resynchronization time after backup system...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Minimizing software downtime associated with software...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Minimizing software downtime associated with software...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Minimum latency reinstatement of database transaction locks

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Minimum memory implementation of high speed viterbi decoder

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Mirror split brain avoidance

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Mirror split brain avoidance

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Mirrored extensions to a multiple disk storage system

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Mirrored memory dual controller disk storage system

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent

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Mirrored volume replication method, apparatus, and system

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Mirroring data between primary and secondary sites

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Mis-synchronization detection system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error count or rate
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Mis-synchronization detection system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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