Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-12-17
2000-11-28
Follansbee, John A.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 38, 714 47, H02H 305, G01R 3128
Patent
active
06154857&
ABSTRACT:
A processor-based device incorporating an on-chip trace cache and supporting circuitry for providing software performance profiling information. A trigger control register is configured to initialize and trigger (start) a first on-chip counter upon entry into a selected procedure. A second trigger control register is used to stop the first counter when the procedure prologue of the selected procedure is entered. Counter values reflecting the lapsed execution time of the selected procedure are then stored in the on-chip trace cache. Similar techniques can be used to measure other parameters such as interrupt handler execution times. In the disclosed embodiment of the invention, a second counter is also provided. The second counter runs continually, but is reset to zero following a stop trigger event caused by the second trigger control register. The stop trigger event also causes the value of the second counter to be placed in the on-chip trace cache. This second counter value is useful for obtaining the frequency of occurrence of a procedure of interest, whereas the first counter provides information about the procedure's execution time. Either post-processing software executing on a target system, a host system utilizing a debug port, or off-chip trace capture hardware can be used to analyze the profile data. Both serial and parallel communication channels are provided for communicating the trace information to external devices. The processor-based device thereby provides a flexible, high-performance solution for furnishing software performance profiling information.
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Advanced Micro Devices , Inc.
Follansbee John A.
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