Clamping divider, processor having clamping divider, and method
Classified adaptive multiple processing system
Clock balanced segmentation digital filter provided with...
Clock divider
Clock signal multiplier circuit for a clock signal generator...
Close path selection unit for performing effective subtraction w
Co-processor for performing modular multiplication
Coefficient update unit
Comb filter system for decimating a sequence of digital...
Combination exerciser gripper and calculator
Combination laptop and pad computer
Combination laptop and pad computer
Combination laptop and pad computer
Combinatorial polynomial multiplier for galois field 256...
Combined adder and logic unit
Combined binary/decimal adder unit
Combined fast fourier transforms and matrix operations
Combined fast multipole-QR compression technique for solving...
Combined interpolation and decimation filter for...
Combined polynomial and natural multiplier architecture