Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Pulse repetition rate
Reexamination Certificate
1999-04-28
2002-02-26
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Pulse repetition rate
C327S116000
Reexamination Certificate
active
06351756
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a clock signal multiplier circuit for a clock signal generator.
The clock signal multiplier circuit is used for multiplying a clock signal frequency to increase the frequency of the externally inputted clock signal. One of the conventional clock signal multiplier circuit is disclosed in Japanese laid-open patent publication No. 2-177715.
FIG. 1
is a circuit diagram illustrative of a first conventional clock signal multiplier circuit. The circuit configuration and operation will be described briefly. A clock signal
101
is inputted into an input terminal of the conventional clock signal multiplier circuit A frequency divider
94
is connected to the input terminal for receiving the input clock signal
101
to generate a frequency increased signal having a higher frequency by two times than the clock signal. A shift resistor circuit
95
is connected to the frequency divider
94
for receiving the frequency increased signal to adjust a duty ratio of the frequency increased signal. The conventional clock signal multiplier circuit generates an output clock signal
118
having a frequency higher by two times than the input clock signal
101
, whereby the conventional clock signal multiplier circuit is capable of two times multiplication in frequency of the inputted lock signal. More detail descriptions will be made as follows.
An oscillator
91
is provided for generating a reference clock signal
201
having a frequency higher by m-times than the frequency of the input clock signal
101
. A counter circuit
92
is provided which is connected to the oscillator
91
for receiving both the input clock signal
101
and the reference clock signal
201
in order to count clock numbers of the reference clock signal
201
within a high level period corresponding to a half cycle which is defined between a rising edge and a failing edge of the input clock signal
101
. The counter circuit
92
counts one clock for the one cycle and generates a counter output signal
202
.
A latch circuit
93
is also provided which is connected to be the counter
92
and the oscillator
91
as well as connected to the input terminal
101
for receiving both the counter output signal
202
from the counter circuit
92
and the input clock signal
101
so that the latch circuit
93
latches a value of the counter output signal
202
in response to the fall-edge of the in put clock signal
101
, in order to generate a latch output signal
203
. The latch circuit
93
continues to latch the value or level of the counter output signal
202
during one cycle of the input clock signal
101
.
A frequency divider
94
is provided which is connected to the latch circuit
93
and the oscillator
91
for receiving both the reference clock signal
201
from the oscillator
91
and the latch output signal
203
from the latch circuit
93
. The frequency divider
94
accommodates a counter, so that the frequency divider circuit
94
generates a frequency dividing signal
204
with the high level and a width corresponding to one cycle of the reference clock signal
201
every when the number of the inputted reference clock signal
201
becomes the same as the number of the counted value which is indicated by the counter output signal
203
. The latch output signal
203
includes an upper significant bat signal
206
and a lower significant bit signal
207
. Namely, the high level signal is outputted one time for every one half cycle of the input clock signal
101
. This means that the frequency divided signal
204
has a frequency higher by two times than the input clock signal
101
.
A shift resistor circuit
95
is also provided which is connected to the frequency divider circuit
94
, the lath circuit
93
and the input terminal for receiving the input clock signal
101
, the upper but signal
206
of the latch output signal
203
and the frequency divided signal
204
, so that every when the shift resistor circuit
95
receives the reference clock signal
201
, then the shift resistor circuit
95
extends the high level period of the frequency divided signal
204
by one cycle of the reference clock signal
201
, whereby the high level period is extended to two cycles, three cycles, four cycles and five cycles. The upper significant bit signal
206
controls the width of extension of the clock As a result, the shift resistor circuit
95
generates a shift resistor output signal
205
having the same one cycle period as the frequency divided signal
204
but different high level period from the frequency divided signal
204
.
If the counted value of the latch circuit
93
is “6”, then a duty ratio of the high level period to the low level period of the frequency divided signal
204
is 1:5, whilst the shift resistor output signal
205
has a different duty ratio of 3:3 from the frequency divided signal
204
. If the counted value of the latch circuit
93
is “5”, then the frequency divided signal
204
has a duty ratio of 1:4, whilst the shift resistor output signal
205
has a different duty ratio of 2:3 from the frequency divided signal
204
.
A flip flop circuit
97
is also provided which is connected to the shift resistor circuit
95
and also connected through an invertor
96
to the oscillator
91
, so that the flip flop circuit
97
receives the sit resistor output signal
205
from the shift resistor circuit
95
and an inverted reference clock signal
208
from the invertor
96
. If the counted value of the latch circuit
93
is odd number, then the flip flop circuit
97
compensates the duty ratio but only of non-50% ratio of the shift resistor output signal
205
. The flip flop circuit
97
is operated to latch the shift resistor output signal
205
in response to the rising edge of the inverted reference clock signal
208
, so that the flip flop circuit
97
performs a logical sum or “OR-operation” of the latched signal and the shift resistor output signal
205
, in order to generate a flip flop output signal
209
which has a high level period extended from the high level period of the shift resistor output signal
205
by one half cycle period of the reference clock signal
201
. If the counted value of the latch circuit
93
is odd number, then the shift resistor output signal
205
has a duty ratio of 2.5:2.5.
A selector
98
is also provided which is connected to both the shift resistor circuit
95
and the flip flop circuit
97
for receiving both the shift resistor output signal
205
and the flip flop output signal
209
, in order to select any one of the shift resistor output signal
205
and the flip flop output signal
209
and outputs the selected one of the shift resistor output signal
205
and the flip flop output signal
209
. The selector
98
is also connected to the latch circuit
93
for receiving the lower significant bit signal
207
of the latch output signal
203
, so that if the lower significant bit signal
207
of the latch output signal
203
is “0”, then the selector
98
selects the shift resistor output signal
205
, whilst if the lower significant bit signal
207
of the latch output signal
203
is “1”, then the selector
98
selects the flip flop output signal
209
. Namely, if the above counted value of the latch circuit
93
is even number, then the selector
98
selects the shift resistor output signal
205
. If the above counted value of the latch circuit
93
is odd number, then the selector
98
selects the flip flop output signal
209
.
Consequently, the above conventional clock signal frequency multiplier circuit is capable of generating two-times multiplied clock signals having a 50% duty ratio to the input clock signal and also having a higher frequency by two times than the input or original clock signals.
The above conventional clock signal frequency multiplier circuit is, however, engaged with the following problems.
The first problem is that the conventional clock signal frequency multiplier circuit is capable of generating but only the two-times multiplied clock signal. In order to obtain four-t
LandOfFree
Clock signal multiplier circuit for a clock signal generator... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Clock signal multiplier circuit for a clock signal generator..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock signal multiplier circuit for a clock signal generator... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2979296