Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2007-09-04
2007-09-04
Mai, Tan V. (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S491000
Reexamination Certificate
active
10615476
ABSTRACT:
Integrated circuit parallel multiplication circuits, including multipliers that deliver natural multiplication products and multipliers that deliver polynomial products with coefficients over GF(2). A parallel multiplier hardware architecture arranges the addition of partial products so that it begins in a first group of adder stages that perform additions without receiving any carry terms as inputs, and so that addition of the carry terms is deferred until a second group of adder stages arranged to follow the first group. This intentional arrangement of the adders into two separate groups allows both the polynomial product to be extracted from the results of the first group of additions, and the natural product to be extracted from the results of the second group of additions.
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Dupaquis Vincent
Paris Laurent
Atmel Corporation
Mai Tan V.
Protsik Mark
Schneck Thomas
Schneck & Schneck
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