Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2002-06-12
2004-12-07
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06829629
ABSTRACT:
The present invention relates to a comb filter arrangement for decimating a sequence of digital input values into a sequence of digital output values by a non-integral factor.
EP 0889587 A1 discloses such a comb filter arrangement which has an input-end integrator whose output is fed to two signal paths, each signal path having an adjustable delay stage and a following decimator stage as well as an output-end differentiator stage. In addition, in this known comb filter arrangement there is a buffer which carries out the function of an interpolation stage.
U.S. Pat. No. 4,999,798 discloses a transient recovery-free interpolation decimator which has one adjustable delay stage and one interpolation stage per signal path.
WO 94/23492 discloses a decimation filter with cascading of at least three signal paths.
In order to recover the clock for conventional modem applications or what are referred to as MDSL applications, decimation by a non-integral factor is often necessary. In sigma-delta analog/digital conversion, comb filter arrangements are generally used for decimation, there being a multiplicity of implementation possibilities for such comb filter arrangements.
A known comb filter arrangement is illustrated in FIG.
1
. However, the comb filter arrangement shown there is suitable only for decimating a sequence of digital input values x
i
into a sequence of digital output values y
j
by an integral factor M. For this purpose, the circuit arrangement according to
FIG. 1
has an input-end integrator
10
of the n-th order, a following decimator stage
124
by the integral factor M and an output-end differentiator
126
, also of the n-th order.
The integrator
10
of the n-th order has n stages which are connected in series, each stage comprising an input-end adder
12
to which two input signals are fed, namely a signal which is fed back via a line
16
and a signal which originates from the signal path and which is the digital input value x
i
in the first stage. The output of the adder
12
is connected to a delay stage
14
. In a following stage, the output of this delay stage
14
forms, on the one hand, the input signal for the adder
12
of this following stage and, on the other hand, also the output of the adder
12
is connected to a delay stage
14
. In a following stage, the output of this delay stage
14
forms, on the one hand, the input signal for the adder
12
of this following stage and, on the other hand, also the signal which is fed back to the assigned adder
12
via the line
16
. For an integrator of the third order, for example three such stages, each with an adder
12
, a delay element
14
and a feedback loop
16
, are necessary.
The output signal of such an integrator
10
of the n-th order is fed to the decimator stage
124
, which filters out, for example, only every tenth incoming sampled value. The output of the decimator stage
124
is connected to the differentiator
126
which has already been mentioned and which also has a predefined number of stages connected in series, in accordance with the order of the differentiator. These stages each have in turn an adder
128
, a delay stage
130
and a line
132
, but, in contrast to the stages of the integrator
10
, they are wired differently. Two input signals, namely on the one hand the signal on the line
132
of the signal path and the signal which is delayed and inverted with respect thereto in the delay stage
130
, are in turn fed to the adder
128
. The output of the adder
128
is then fed to the one input of the adder
128
of a following stage, and also to the delay stage
130
there. Three such stages connected in series are necessary in order to implement a differentiator of the third order.
Such a comb filter arrangement is suitable for decimating the sequence of digital input values x
l
by an integral factor M, for example 10.
The invention is based on the object of developing the comb filter arrangement which is described in FIG.
1
and is known, in such a way that it is possible to decimate the sequence of digital input values x
i
by a non-integral factor.
This object is achieved by means of a comb filter arrangement having the features of claim
1
.
Developments of the comb filter arrangement are the subject matter of the subclaims.
According to the invention, an input-end integrator of the n-th order, whose output is fed to at least three signal paths, is accordingly provided. Each signal path has a delay stage with a delay which can be set to different values, a following decimator stage by an integral factor M, and an output-end differentiator stage for generating intermediate output values. An interpolation arrangement, at whose output the sequence of digital output values y
j
which are decimated by the non-integral factor can be tapped, is connected to the output of the three signal paths.
The interpolation arrangement is constructed in such a way that it always interpolates between two intermediate output values which are present at the output end on the three signal paths and have an interval of k/f (f=sampling rate and k=delay factor). The interpolation is expediently a linear interpolation.
The differentiator stages of the individual signal paths operate according to the invention with a sampling rate which is reduced by the factor M, as a result of which the expenditure on adders and delay elements is advantageously low. In order to achieve the non-integral change in the sampling rate, the interpolation is carried out according to the invention between two intermediate output values which are delayed by the respective signal paths.
In one embodiment of the invention, the interpolation arrangement has two switch-over devices whose three inputs are each connected to an output of the three differentiator stages and whose outputs are each connected to one amplifier. Furthermore, an adder stage is provided for adding the output signals of the two amplifiers.
A further embodiment of the invention provides a control device for switching over the switch-over devices in each case in accordance with the two intermediate output signal values to be interpolated.
Another embodiment of the invention provides for the interpolation arrangement to carry out a linear interpolation in accordance with
y
j
=&agr;·y
i+l
+(1−&agr;)·
y
i
or
y
j
=&agr;y
i+k
+(1−&agr;)·y
i+3k
For this purpose, only two multiplication operations and one addition operation are required within the interpolation arrangement at the low sampling rate. After a predefined number of such interpolation operations, the system is switched over to interpolation, as stated in the above formulae, between the two value pairs (y
i
, y
i+k
) and the value pair (y
i+k,
Y
i+2k
).
A very central feature of the comb filter arrangement according to the present invention is the fact that only two value pairs are required for interpolation. Because n differentiators are provided in the respective signal paths after the decimator stage in the comb filter arrangement according to the invention, the comb filter arrangement requires n steps for transient recovery so that only the n+1-th output value after the switching over in the switch-over devices can be used by the input sequence. For this reason, each differentiator chain in the signal paths must already be phased in n steps before it is connected to the output.
It is of crucial significance in the comb filter arrangement according to the invention that the interpolation always takes place between two values which are at an interval of k·T (T=1/f, f=high sampling rate). As a result, in all cases it is possible to interpolate k times between the value pairs (y
i
, y
i+k
) without requiring a new support point. These are precisely those k steps which are required by a chain of k differentiators for the transient recovery and/or which are required in order to calculate the values of the k registers of the differentiators. The output value of the differentiator chain can then alread
Caldera Peter
Gazsi Lajos
Magesacher Thomas
Fish & Richardson P.C.
Infineon - Technologies AG
Mai Tan V.
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