Combined adder and logic unit

Details Combined adder and logic unit Combined adder and logic unit

1997-11-13

1999-08-31

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708714, G06F 750

Patent

active

059447729

ABSTRACT:
A combined adder and logic unit having a reduced operation delay of arithmetic and logic operations, and providing an improved fan in and reduced wiring delays and capacity if implemented in the arithmetic and logic section of a microprocessor chip. The unit comprises a carry network (30) connected to operand inputs for generating carry-out signals of the byte positions (By0-By7) and further comprises a pre-sum logic (32) having a bit function generator (42) and a sum generator (45, 46, 48). Said bit function generator derives from the operands Ai and Bi bit functions Gi, Pi which are provided as logic function output and as input to said sum generator for producing preliminary arithmetic functions (SUM0, SUM1) to anticipate carry-in signals of one or zero. A result selector (70) is controlled by a byte position carry-out signal (Cy55) from the carry network means and by operation control signals to select from the output of said pre-sum logic one of the arithmetic functions (SUM0, SUM1) or one of the logic functions as result of the unit operation.

REFERENCES:
patent: 5299319 (1994-03-01), Vassiliadis et al.
patent: 5487025 (1996-01-01), Partori et al.
patent: 5764550 (1998-06-01), D'Sovza

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