Combined binary/decimal adder unit

Details Combined binary/decimal adder unit Combined binary/decimal adder unit

1997-11-13

1999-07-27

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 750

Patent

active

059283190

ABSTRACT:
A combined binary/decimal adder unit reduces the operation delay ine processing binary coded decimal operands and permit an increased cycle rate of a processor unit in which the combined binary/decimal adder unit is utilized. Pre-sums are generated for each decimal digit position in parallel to the generation and distribution of the carries over the total of decimal digit positions of the adder unit. The pre-sums anticipate the carry-in of the decimal positions and the need to perform six corrections after the carry-out signal of the highest decimal digit position has been generated. The carry-out signal of each decimal digit position is used in combination with operation control signals to select the correct pre-sum of the digit position.

REFERENCES:
patent: 5007010 (1991-04-01), Flora
patent: 5146423 (1992-09-01), Fischer et al.
patent: 5745399 (1998-04-01), Eaton et al.

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