Layout structure for barrel shifter with decode circuit

Details Layout structure for barrel shifter with decode circuit Layout structure for barrel shifter with decode circuit

1997-10-28

1999-08-24

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 501

Patent

active

059419377

ABSTRACT:
Two flip-flops and decode circuits are provided. Whereas the one flip-flop receives 1-bit bit-shift-amount data B(1), the other flip-flop receives 1-bit bit-shift-amount data B(0). The decode circuits decode the bit-shift-amount data from the flip-flops. The flip-flops and the decode circuits are laterally laid out in a line. The flip-flops and the decode circuits are symmetrically laid out in bits, together with four flip-flops that receive respective 1-bit data to be bit-shifted (data A(3) to A(0)) and a bit shifter that bit-shifts the data A(3) to A(0) for a bit shift amount from said decode circuits, to form a bit slice structure and to be arranged within a data path. Accordingly, it is possible to achieve an effective reduction of the length of signal wiring over which bit-shift-amount data propagate. The reduction of wire load can be accomplished. The speed-up of data bit shift processing can be realized.

REFERENCES:
patent: 4653019 (1987-03-01), Hodge et al.
patent: 5465223 (1995-11-01), Nishimura
patent: 5477477 (1995-12-01), Saitou
patent: 5652718 (1997-07-01), Thomson et al.
patent: 5777906 (1998-07-01), Lav et al.

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