Leading Zero Anticipatory (LZA) algorithm and logic for high...

Details Leading Zero Anticipatory (LZA) algorithm and logic for high... Leading Zero Anticipatory (LZA) algorithm and logic for high...

2006-04-04

2006-04-04

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S505000

Reexamination Certificate

active

07024439

ABSTRACT:
Method and apparatus are described for anticipating the number of leading zeros or leading ones in a sum of mantissas irrespective of the sign of the result or the relative magnitudes of the input operands using a leading zero anticipation (LZA) device. An algorithm is presented for leading zero and leading one anticipation that may be used to remove leading zeroes or ones from sums produced in arithmetic units. This algorithm and the design of the combinational logic does not require a comparison of input operands nor does it need two separate counters for leading zeros and leading ones as in most other LZAs. The present invention is especially applicable to redundant format addition.

REFERENCES:
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patent: 6178437 (2001-01-01), Dhong et al.
patent: 6205461 (2001-03-01), Mansingh
patent: 6405232 (2002-06-01), Green et al.
patent: 6499044 (2002-12-01), Brooks et al.
patent: 6594679 (2003-07-01), Lee et al.
patent: 6779008 (2004-08-01), Erle et al.

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