Linear function generator method with counter for implementation

Details Linear function generator method with counter for implementation Linear function generator method with counter for implementation

1997-08-28

2000-03-21

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 1711

Patent

active

060413379

ABSTRACT:
A method for using linear functions with counter modules for efficient implementation in PALs (Programmable Array Logic), or FPGAs (Field Programmable Gate Arrays) which generate digital control signals to a targeted digital device.
An input setting pulsed digital signal A is upcounted and then is reduced by a downcounted feedback pulsed digital signal to produce a difference digital signal which involves adding an intercept value. The difference signal is multiplied by a slope-sensitivity parameter, each time expanding the numeric range and scope of the output digital control signal to the target digital device.

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patent: 5189314 (1993-02-01), Georgiou et al.
patent: 5793380 (1998-08-01), Matsumo

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