Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-03-15
2002-03-19
Malzahn, David H. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S211000
Reexamination Certificate
active
06360238
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to an apparatus for data processing in general, and in particular to an apparatus for performing result normalization in a floating-point processor. Still more particularly, the present invention relates to a leading zero/one anticipator in a floating-point processor.
2. Description of the Prior Art
According to the. IEEE 754 standard, floating-point numbers are represented by three elements, namely, a binary sign bit, a binary encoded exponent, and a binary encoded mantissa. In a normalized floating-point number, the exponent is that which ensures the first digit of the mantissa is a logical one (except for special cases such as zero, infinities, and unrepresentable numbers). During a normalized floating-point addition, one of the mantissas of the addend and adder is shifted and the exponent is incremented or decremented until the exponents for both the addend and adder are equal. This shifting process is known as alignment. Once aligned, the mantissas of the addend and adder are added or subtracted depending upon the signs of the addend and adder as well as the type of operation (either addition or substraction) to be performed. Once the result (either sum or difference) is formed, the sign of the resulting mantissa is examined. If the sign of the result is negative, the boolean complement of the result is initially formed, and the sign is then complemented. In order to convert the result to a normalized form, the exponent of the result is decremented and the mantissa of the result is left-shifted until the leading digit of the mantissa is a logical one (in absence of exceptional conditions such as those mentioned supra).
The processing of removing leading zeros or leading ones from a respective positive or negative output of a floating-point adder is known as normalization. Full-precision leading-zero anticipators (LZAs) (or leading-zero predictors) are commonly utilized to improve the speed of a normalization process. An LZA can be the most critical path of a floating-point adder because it is not obvious a priori whether the result from the adder will be positive or negative. Thus, it is necessary to perform both leading-zero and leading-one analysis so that a proper normalization shift amount can be selected based upon the sign of the result when the result is finally available.
The prior art process of sign determination is typically accomplished via a floating-point adder. With the improved LZA architecture as disclosed in the above-mentioned related patent application, the prior art process of sign determination becomes the bottle-neck of a normalization process. The present disclosure describes an improved sign determination mechanism that complements the LZA described in the above-mentioned related patent application.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a leading zeros string and a leading ones string are generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is then determined from the leading zeros string and the leading ones string. A sign of a sum of the two input operands is then determined separately but concurrently with the normalization shift amount determination process. The sign is then utilized to select either the positive sum or the negative sum for a proper normalization shift amount.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5633819 (1997-05-01), Brashears et al.
patent: 5920493 (1999-07-01), Lau
patent: 5974432 (1999-10-01), Orup
patent: 6085208 (2000-07-01), Oberman et al.
patent: 6101516 (2000-08-01), Wolrich et al.
Dhong Sang Hoo
Lee Kyung Tek
Ngo Hung Cai
Nowka Kevin John
Bracewell & Patterson L.L.P.
International Business Machines - Corporation
Malzahn David H.
Salys Casimer K.
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