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Set-associative cache memory having a mechanism for...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Set-associative cache memory having asymmetric latency among...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Set-associative cache memory having incremental access...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Set-associative cache memory having variable time decay...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Set-associative cache memory utilizing a single bank of physical

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Set-associative cache using cache line decay counts and set...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Set-associative cache using cache line decay counts and set...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Set-associative cache-management method with parallel and...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Set-associative cache-management method with parallel and...

Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
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Set-associative cache-management method with parallel read...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Set-associative cache-management using parallel reads and...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Shader cache using a coherency protocol

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Shadow commands to optimize sequencing of requests in a...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Shadow mechanism for a modifiable object oriented system

Electrical computers and digital processing systems: memory – Storage accessing and control
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Shadow page tables for address translation control

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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Shadow register to enhance lock acquisition

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Sharding method and apparatus using directed graphs

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Share masks and alias for directory coherency

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Share masks and alias for directory coherency

Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
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Shared buffer having hardware-controlled buffer regions

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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