Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-07-01
2008-07-01
Bragdon, Reginald G. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S128000, C711S134000, C711S136000, C711S144000, C711S202000
Reexamination Certificate
active
07395373
ABSTRACT:
Embodiments of a method for reducing conflict misses in a set-associative cache by mapping each memory address to a primary set and at least one overflow set are described. If a conflict miss occurs within the primary set, a cache line from the primary set is selected for replacement. However, rather than removing the selected cache line from the cache completely, the selected cache line may instead be relocated to the overflow set. The selected cache line replaces a cache line in the overflow set, if it is determined that the selected cache line from the primary set has an estimated age that is more recent than an estimated age for any cache line in the overflow set. Embodiments of the method incorporate various techniques for estimating the age of cache lines, and, particularly, for estimating the relative time since any given cache line was last accessed.
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Bragdon Reginald G.
Gibb & Rahman, LLC
Gu Shawn X
International Business Machines - Corporation
Nelson, Esq. Eustus D.
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