4. Electrical computers and digital processing systems: memory
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Pseudo-LRU for a locking cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate

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Pseudo-random address generation mechanism that reduces address

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Patent

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Pseudorandom data storage

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate

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Pulsed Y-decoders for improving bitline precharging in memories

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...
Patent

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Purge control for ON-chip cache memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent

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Pushing of clean data to one or more processors in a system...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate

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Pushing of clean data to one or more processors in a system...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate

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