Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-05-30
2006-05-30
Peikari, B. James (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S160000, C711S133000, C711S134000, C711S159000, C707S793000
Reexamination Certificate
active
07055004
ABSTRACT:
The present invention provides for a cache-accessing system employing a binary tree with decision nodes. A cache comprising a plurality of sets is provided. A locking or streaming replacement strategy is employed for individual sets of the cache. A replacement management table is also provided. The replacement management table is employable for managing a replacement policy of information associated with the plurality of sets. A pseudo least recently used function is employed to determine the least recently used set of the cache, for such reasons as set replacement. An override signal line is also provided. The override signal is employable to enable an overwrite of a decision node of the binary tree. A value signal is also provided. The value signal is employable to overwrite the decision node of the binary tree.
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DeMent Jonathan James
Hall Ronald
Liu Peichun Peter
Truong Thuong Quang
Carr LLP
Gerhardt Diana R.
Peikari B. James
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