Purge control for ON-chip cache memory

Details Purge control for ON-chip cache memory Purge control for ON-chip cache memory

1997-07-01

1998-09-15

Pan, Daniel H.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711214, 711203, 711135, G06F 9312, G06F 9445, G06F 1210

Patent

active

058092749

ABSTRACT:
A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instructioon is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output the instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

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