Pulsed Y-decoders for improving bitline precharging in memories

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...

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365203, 36523003, G06F 1200

Patent

active

060981458

ABSTRACT:
A memory system is accessed and precharged by accessing adjacent columns in the memory array with a pulsed select signal in a first state and then enabling precharge circuitry to precharge the adjacent columns using the same select signal in a second state. Latches, coupled to the outputs of the sense amplifiers sensing the data from the adjacent cells, are also controlled by a pulsed signal synchronized with the select signal such that at the same time the adjacent columns are selected and accessed, the latches detect the data sensed by their corresponding sense amplifier. Once the select signal changes to its second state, the adjacent columns are deselected and the latches are disabled such that the data sensed from the adjacent columns is saved by the latches and provided to the output of the memory system and such that the precharge circuitry is enabled and the adjacent column bitlines are precharged. Access cycle times are reduced by accessing and precharging small sets of adjacent columns such that precharge takes less time and occurs immediately after cells have been accessed.

REFERENCES:
patent: 4881203 (1989-11-01), Watanabe et al.
patent: 4972373 (1990-11-01), Kim et al.
patent: 5193076 (1993-03-01), Houston
patent: 5631871 (1997-05-01), Park et al.
patent: 5917744 (1999-06-01), Kirihata et al.

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