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Dependency checking structure for a pair of caches which are acc

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dependency controller and method for overlapping memory...

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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Dependent bank memory controller method and apparatus

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
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Design architecture for a parallel and serial programming...

Electrical computers and digital processing systems: memory – Storage accessing and control
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Design of tags for lookup of non-volatile registers

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Design structure for content addressable memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Design structure for selecting memory busses according to...

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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Designing a cache using an LRU-LFU array

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Designing a cache with adaptive reconfiguration

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Destage management of redundant data copies

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Destage of data for write cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Destaging method for storage apparatus system, and disk...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Destination indexed miss status holding registers

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Destructive read architecture for dynamic random access...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Destructive read protection using address blocking technique

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Destructive-read random access memory system buffered with...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Destructive-read random access memory system buffered with...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Destructive-read random access memory system buffered with...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Detachable memory apparatus capable of varying number of wait st

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Detachably mounted removable data storage device

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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