Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-08-21
1998-07-28
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
364DIG1, 364DIG2, 3642434, 711 3, 711118, 711146, G06F 1200, G06F 1208
Patent
active
057874654
ABSTRACT:
A hierarchical memory arrangement for use with a processor includes a cache, addressable by source addresses, and a set of processor registers, addressable by destination addresses. For each processor register there is a miss status holding registers. If the cache does not store data requested for one of the processor registers, a miss condition is generated. In response to the miss condition, the address of a cache block to contain the missing data is stored in the miss status holding register corresponding to the processor register for which the data are requested. While the requested data are transferred from a main memory to the cache, the cache is not locked up and additional data accesses are allowed.
REFERENCES:
patent: Re34052 (1992-09-01), Hester et al.
patent: 4370710 (1983-01-01), Kroft
patent: 4646233 (1987-02-01), Weatherford
patent: 4970643 (1990-11-01), Cramm
patent: 5148536 (1992-09-01), Witek et al.
patent: 5233702 (1993-08-01), Emma et al.
patent: 5261066 (1993-11-01), Jouppi
patent: 5295253 (1994-03-01), Ducousso et al.
patent: 5377345 (1994-12-01), Chang et al.
Kroft, D., "Lockup-Free Instruction Fetch/Prefetch Cache Organization", 1981 IEEE, pp. 81-87.
"Memory Access Dependencies in Shared Memory Multiprocessors", M. Dubois and C. Scheurich, IEEE Trans. Software Eng., Jun. 1990.
"The Design of a Lookup-Free Cache", M. Dubois and c. Scheurich, IEEE, 1990, pp. 352-389.
"Lockup-Free Caches in High Performance Multiprocessors", C. Scheurich and M. Dubois, J. of Parallel and Distributed Computing, vol. 11, 1991, pp. 25-36.
Haddad Ramsey W.
Jouppi Norman P.
Brinkman Dirk
Digital Equipment Corporation
Johnston A. Sidney
Stadnicki Alfred A.
Swann Tod R.
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