Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-04-26
2004-12-07
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S141000, C711S142000, C711S144000, C711S133000, C711S134000, C711S105000
Reexamination Certificate
active
06829682
ABSTRACT:
BACKGROUND
The present invention relates generally to integrated circuit memory devices and, more particularly, to improving access cycle time for Dynamic Random Access Memories (DRAMs).
The evolution of sub-micron CMOS technology has resulted in significant improvement in microprocessor speeds. Quadrupling roughly every three years, microprocessor speeds have now even exceeded 1 Ghz. Along with these advances in microprocessor technology have come more advanced software and multimedia applications, requiring larger memories for the application thereof. Accordingly, there is an increasing demand for larger Dynamic Random Access Memories (DRAMs) with higher density and performance.
DRAM architectures have evolved over the years, being driven by system requirements that necessitate larger memory capacity. However, the speed of a DRAM, characterized by its random access time (tRAC) and its random access cycle time (tRC), has not improved in a similar fashion. As a result, there is a widening speed gap between the DRAMs and the CPU, since the clock speed of the CPU steadily improves over time.
The random access cycle time (tRC) of a DRAM array is generally determined by the array time constant, which represents the amount of time to complete all of the random access operations. Such operations include: wordline activation, signal development on the bitlines, bitline sensing, signal write back, wordline deactivation and bitline precharging. Because these operations are performed sequentially in a conventional DRAM architecture, increasing the transfer speed, or bandwidth, of the DRAM becomes problematic.
BRIEF SUMMARY
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a method for controlling the operation of a dynamic random access memory (DRAM) system, the DRAM system having a plurality of memory cells organized into rows and columns. In an exemplary embodiment of the invention, the method includes enabling a destructive read mode, the destructive read mode for destructively reading a bit of information stored within an addressed DRAM memory cell. The destructively read bit of information is temporarily stored into a temporary storage device. A delayed write back mode is enabled, the delayed write back mode for restoring the bit of information back to the addressed DRAM memory cell at a later time. The execution of the delayed write back mode is then scheduled, depending upon the availability of space within the temporary storage device.
In a preferred embodiment, enabling a destructive read mode includes developing a differential signal on a pair of precharged complementary bit lines, one of the bit lines being coupled to the addressed DRAM memory cell. The differential signal is then transferred the pair of bit lines to a pair of sense lines, with the sense lines being isolated from the bit lines immediately thereafter. Then, the pair of bit lines is precharged.
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Dhong Sang Hoo
Kirihata Toshiaki
Oh Hwa-Joon
Wordeman Matthew
Cantor & Colburn LLP
International Business Machines - Corporation
Nguyen T
Walsh Robert A.
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