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Demand-based error correction

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Demand-based issuance of cache operations to a processor bus

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Demand-based larx-reserve protocol for SMP system buses

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Demand-based memory-block splitting

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Demand-driven opportunistic garbage collection in memory...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Demoting tracks from cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Demotion of memory pages to largest possible sizes

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Dense edit re-recording to reduce file fragmentation

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Dense server environment that shares an IDE drive

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Dependency checking structure for a pair of caches which are acc

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dependency controller and method for overlapping memory...

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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Design architecture for a parallel and serial programming...

Electrical computers and digital processing systems: memory – Storage accessing and control
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Design of tags for lookup of non-volatile registers

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Design structure for content addressable memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Designing a cache using an LRU-LFU array

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Designing a cache with adaptive reconfiguration

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Destage management of redundant data copies

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Destage of data for write cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Destaging method for storage apparatus system, and disk...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Destination indexed miss status holding registers

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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